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preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 1 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 4gb ddr3 C registered ecc r dimm 240 pin registered dimm sgp04g72a1bd1sa - xx r t 4 g b in fbga tech nology rohs compliant *) the refresh rate has to be doubled when 85c preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 2 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 this swissbit module is an industry standar d 240 - pin 8 - byte ddr3 registered sdram dual - in - line memory module ( r dimm) which is organized as x 72 high speed cmos memory arrays. the module uses internally configured oct al - bank ddr3 sdram devices. the module uses double data rate architecture to achieve high - speed operation. ddr3 sdram modules operate from a differential clock (ck and ck#). read and write accesses to a ddr3 sdram module is burst - oriented; accesses start at a selected location and continue for a programmed number of locations in a program med sequence. the burst length is either four or eight locations. an auto precharge function can be enabled to provide a self - timed row precharge that is initiated at the end of a burst access. the ddr3 sdram devices have a multibank architecture which all ows a concurrent operation that is providing a high effective bandwidth. a self refresh mode is provided and a power - saving power - down mode. all inputs and all full drive - strength outputs are sstl_15 compatible. the ddr3 sdram module uses the serial pres ence detect (spd) function implemented via serial eeprom using the standard i 2 c protocol. this nonvolatile storage device contains 256 bytes. the first 128 bytes are utilized by the dimm manufacturer (swissbit) to identify the module type, the modules org anization and several timing parameters. the second 128 bytes are available to the end user. module configuration organization ddr3 sdrams used row addr. device bank addr. col umn . addr. refresh module bank select 512 m x 72 bit 9 x 512 m x 8bit ( 4 gbit) 1 6 b a0, ba1, ba2 10 8k s0# module dimensions in mm 133.35 (long) x 30 (high) x 4.0 [max] (thickness) timing parameters part number module density transfer rate clock cycle/data bit rate latency sgp04g72a1bd1sa - d c rt 4 gb yte 12.8 gb/s 1.25ns/1600mt/s 11 - 11 - 11 pin name a0 C a9, a11, a13 C a1 5 address inputs (a15 not functional, but included in parity check) a10/ap address input / auto precharge bit a12/bc address input / burst chop ba0 C ba2 bank address inputs dq0 C dq63 data input / output cb0 C c b7 data check bits input / output dqs0 C dqs8 data strobe, positive line dqs0# C dqs8# data strobe, negative line (only used when differential data strobe mode is enabled) tdqs9 - 17, tdqs9 - 17# redundant data strobe (x8 devices only): when tdqs is enabled via emrs, dm is disabled and tdqs / tdqs# provide termination resistance for x4 based modules s0# chip select ras# row address strobe cas# column address strobe we# write enable cke0 clock enable ck0 C ck1 clock inputs, positive line figure 1: mechanical dimensions
preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 3 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ck0# C ck1# cl ock inputs, negative line event# temperature event: the event# pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded v dd supply voltage (1.5v 0.075v) v ref dq reference voltage: dq, dm (v dd /2) v ref ca reference voltage: control, command, and address (v dd /2) v ss ground v tt termination voltage: used for control, command, and address (v dd /2). v ddspd serial eeprom positive power supply (3.0 - 3.6v) scl serial clock for presence detect sda serial data out for pres ence detect sa0 C sa2 serial presence detect address inputs odt0 on - die termination nc / nu no connection / not used pin configuration frontside pin symbol pin symbol pin symbol pin symbol pin symbol 1 v ref dq 27 dq18 49 v tt 75 v dd 101 v ss 2 v ss 28 dq19 50 cke0 76 nc ( s1# ) * 102 dqs6# 3 dq0 29 v ss 51 v dd 77 nc ( odt1 )* 103 dqs6 4 dq1 30 dq24 52 ba2 78 v dd 104 v ss 5 v ss 31 dq25 53 err_out# 79 nc ( s2# ) * 105 dq50 6 dqs0# 32 v ss 54 v dd 80 v ss 106 dq51 7 dqs0 33 dqs3# 55 a11 81 dq32 107 v ss 8 v ss 3 4 dqs3 56 a7 82 dq33 108 dq56 9 dq2 35 v ss 57 v dd 83 v ss 109 dq57 10 dq3 36 dq26 58 a5 84 dqs4# 110 v ss 11 v ss 37 dq27 59 a4 85 dqs4 111 dqs7# 12 dq8 38 v ss 60 v dd 86 v ss 112 dqs7 13 dq9 39 cb0 61 a2 87 dq34 113 v ss 14 v ss 40 cb1 62 v dd 88 dq35 114 d q58 15 dqs1# 41 v ss 63 rfu 89 v ss 115 dq59 16 dqs1 42 dqs8# 64 rfu 90 dq40 116 v ss 17 v ss 43 dqs8 65 v dd 91 dq41 117 sa0 18 dq10 44 v ss 66 v dd 92 v ss 118 scl 19 dq11 45 cb2 67 v ref ca 93 dqs5# 119 sa2 20 v ss 46 cb3 68 par_in 94 dqs5 120 v tt 21 dq16 4 7 v ss 69 v dd 95 v ss 22 dq17 48 v tt 70 a10/ ap 96 dq42 23 v ss 71 ba0 97 dq43 24 dqs2# 72 v dd 98 v ss 25 dqs2 73 we# 99 dq48 26 v ss 74 cas# 100 dq49
preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 4 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 backside pin symbol pin symbol pin symbol pin symbol pin symbol 121 v ss 147 dq23 169 nc ( cke1 ) * 195 odt0 221 t dqs15 122 dq4 148 v ss 170 v dd 196 a13 222 t dqs15# 123 dq5 149 dq28 171 a15 197 v dd 223 v ss 124 v ss 150 dq29 172 a14 198 nc ( s3# ) * 224 dq54 125 t dqs9 151 v ss 173 v dd 199 v ss 225 dq55 126 t dqs9# 152 t dqs12 174 a12, bc 2 00 dq36 226 v ss 127 v ss 153 t dqs12# 175 a9 201 dq37 227 dq60 128 dq6 154 v ss 176 v dd 202 v ss 228 dq61 129 dq7 155 dq30 177 a8 203 t dqs13 229 v ss 130 v ss 156 dq31 178 a6 204 t dqs13# 230 t dqs16 131 dq12 157 v ss 179 v dd 205 v ss 231 t dqs16# 132 dq13 158 cb4 180 a3 206 dq38 232 v ss 133 v ss 159 cb5 181 a1 207 dq39 233 dq62 134 t dqs10 160 v ss 182 v dd 208 v ss 234 dq63 135 t dqs10# 161 t dqs17 183 v dd 209 dq44 235 v ss 136 v ss 162 t dqs17# 184 ck0 210 dq45 236 v ddspd 137 dq14 163 v ss 185 ck0# 211 v ss 237 sa1 138 dq15 164 cb6 186 v dd 212 t dqs14 238 sda 139 v ss 165 cb7 187 event# 213 t dqs14# 239 v ss 140 dq20 166 v ss 188 a0 214 v ss 240 v tt 141 dq21 167 nc(test) 189 v dd 215 dq46 142 v ss 168 reset# 190 ba1 216 dq47 143 t dqs11 191 v dd 217 v ss 144 t dqs 11# 192 ras# 218 dq52 145 v ss 193 s0# 219 dq53 146 dq22 194 v dd 220 v ss *) following pin functions are depending on module configuration: ? s1# is connected, but not used functionally for single rank dimms ? odt1, cke1 are not used for single r ank modules ? s2# and s3# are only used for quad rank modules ? event# is only used with temperature sensor equipped modules ? a13, a14, a15 are included in parity calculation. function depends on dram address configuration. a13 used for 1gb, a13 & a14 for 2gb, a13 - a15 for 4gb sdram
preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 5 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 functional block diagramm 4096 mb ddr3 sdram r dimm, 1 rank and 9 components
preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 6 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 maximum electrical dc characteristics parameter/ condition symbol min max units v dd supply voltage relative to v ss v dd - 0.4 1.975 v i/o v dd supply voltage relative to v ss v dd q - 0.4 1.975 v voltage on any pin relative to v ss v in , v out - 0.4 1.975 v input leakage current any input 0v v in v dd, v ref pin 0v v in 0.95v (all other pins not under test = 0v) i i a command/address ras#, cas#, we#, s#, cke - 16 16 ck, ck# - 16 16 dm - 2 2 output leakage current (dqs and odt are disabled; 0v v out v dd q ) i oz - 5 5 a dq, dqs, dqs# v ref leakage current ; v ref is on a valid level i vref - 8 8 a dc operating conditions parameter/ condition symbol min nom max units supply voltage v dd 1.425 1.5 1.575 v i/o supply voltage v dd q 1.425 1.5 1.575 v v dd l suppl y voltage v dd l 1.425 1.5 1.575 v i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt 0.49 x v dd q - 20mv 0.50 x v dd q 0.51x v dd q +20mv v input high (logic 1) voltage v ih (dc) v ref + 0.1 v dd q + 0.3 v input low (logic 0) voltage v il (dc) - 0.3 v ref C ac input operating conditions parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.175 - v input low (logic 0) voltage v il (ac) - v ref - 0.175 v capacitance at ddr3 data rates, it is recommended to simulate the performance of the module to achieve optimum values. when inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gr oss estimation of module capacitance. simulations can then render a considerably more accurate result. jedec modules are now designed by using simulations to close timing budgets.
preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 7 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 i dd specifications and conditions (0c t case + 85c; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) parameter & test condition symbol max. unit 12800 cl11 10600 cl9 operating current *) : one device bank active - precharge; t rc = t rc (i dd ); t ck = t ck (i dd ); cke is high, cs# is high between valid commands; dq inputs cha nging once per clock cycle; address and control inputs changing once every two clock cycles i dd0 1098 1030 ma operating current *) : one device bank; active - read - precharge; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address inputs changing once every two clock cycles; data pattern is same as i dd4w i dd1 1197 1129 ma precharge power - down current: all device banks idle; power - down mode ; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref fast exit i dd2p 828 778 ma slow exit 828 778 precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# i s high; all control and address bus inputs are not changing; dqs are floating at v ref i dd2q 886 846 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd2n 924 884 ma active power - down current: all device banks open; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref (always f ast exit) i dd3p 828 778 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clo ck cycles; dq inputs changing once per clock cycle i dd3n 1094 1018 ma operating read current: all device banks open, continuous burst reads; one module rank active; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4r 1494 1354 ma
preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 8 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 parameter & test condition symbol max. unit 12800 cl11 10600 cl9 operating write current: all device banks open, continuous burst writes; one module rank active; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus i nputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4w 1504 1364 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval, cke is high, cs# is high between valid commands; all other con trol and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd5 2579 2539 ma self refresh current: ck and ck# at 0v; cke 0.2v; all other control and address bus inputs are floating at v ref ; dqs are floating at v ref i dd6 300 300 ma operating current*) : four device bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) C 1 x t ck (i dd ); t ck = t ck (i d d ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are not changing during deselect; dq inputs changing once per clock cycle i dd7 2034 1948 ma *) value calculated as one module r ank in this operating condition, and all other module ranks in idd2p (cke low) mode. timing values used for i dd measurement i dd measurement conditions symbol 12800 cl11 10600 cl9 unit cl (i dd ) 11 9 t ck t rcd (i dd ) 13.75 13.5 ns t rc (i dd ) 48.75 49.5 ns t rrd (i dd ) 6.25 6 ns t ck (i dd ) 1.25 1.5 ns t ras min (i dd ) 35 36 ns t ras max (i dd ) 70200 70200 ns t rp (i dd ) 13.75 13.5 ns t rfc (i dd ) 2 60 2 60 ns
preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 9 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ddr3 sdram component electrical characteristics and recommended ac operating conditions (0c t case + 85c; v dd q = +1.5v 0.075v, v dd = +1. 5v 0.075v) ac characteristics 12800 cl11 10600 cl9 parameter symbol min max min max unit clock cycle time cl = 11 t ck (11) 1.25 1.5 - - ns cl = 10 t ck (10) 1.5 <1.875 1.5 <1.875 ns cl = 9 t ck (9) 1.5 <1.875 1.5 <1.875 ns cl = 8 t ck (8) 1.875 <2.5 1.875 <2.5 ns cl = 7 t ck (7) 1.875 <2.5 1.875 <2.5 ns cl = 6 t ck (6) 2.5 3.3 2.5 3.3 ns cl = 5 t ck (5) 3.0 3.3 3.0 3.3 ns read cmd to 1 st data t aa 13.75 - 13.5 - ns ck high - level width t ch (avg) 0.47 0.53 0.47 0.53 t ck ck low - level width t cl (avg) 0.47 0.53 0.47 0.53 t ck data - out high - impedance window from ck/ck# t hz - 225 - 250 ns data - out low - impedance window from ck/ck# t lz - 450 225 - 500 250 ns dq and dm input pulse width ( for each input ) t dipw 360 - 400 - ns dq - dqs hold, dqs to first dq to go non - valid, per access t qh 0.38 - 0.38 - t ck (avg) dqs input high pulse width t dqsh 0.45 0.55 0.45 0.55 t ck dqs input low pulse width t dqsl 0.45 0.55 0.45 0.55 t ck dqs read preamble t rpre 0.9 not e 1 0.9 note 1 t ck dqs read postamble t rpst 0.3 note 2 0.3 note 2 t ck dqs write preamble t wpre 0.9 - 0.9 - t ck dqs write postamble t wpst 0.3 - 0.3 - t ck 1 the maximum preamble is bound by t lzdqs (max) 2 the maximum postamble is bound by t hzdqs (max) the dq, d qs setup and hold times as well as command/address setup and hold times need to be calculated using the respective component data sheets with derating tables and the driver slew rate in combination with the jedec min/max routing information
preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 10 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ddr3 sdram com ponent electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 12800 cl11 10600 cl9 parameter symbol min max min max unit cas# to cas# command delay t ccd 4 - 4 - t ck active to active (same bank) command period t rc 48.75 - 49. 5 - ns active bank a to active bank b command t rrd max 4nck,6ns - max 4nck, 6 ns - ns active to read or write delay t rcd 13.75 - 13.5 - ns four bank activate period 1k page size t faw 30 - 30 - ns 2k page size 40 - 45 - active to precharge command t ra s 35 70200 70200 t rtp max 4nck,7.5ns - max 4nck,7.5ns - ns write recovery time t wr 15 - 15 - ns auto precharge write recovery + precharge time t dal t wr + t rp /t ck - t wr + t rp /t ck - ns internal write to r ead command delay t wtr max 4nck,7.5ns - max 4nck,7.5ns - ns precharge command period t rp 13.75 - 13.5 - ns load mode command cycle time t mrd 4 - 4 - t ck refresh to active or refresh to refresh command interval t rfc 260 70200 70200 0 c t case 85 c t refi - 7.8 - 7.8 s 85 c < t case 95 c t refi (it) - 3.9 - 3.9 rtt turn - on from odtl on reference t aon - 2 25 2 25 - 250 250 ps rtt turn - on from odtl off reference t aof 0.3 0.7 0.3 0.7 t ck asynchronous rtt turn - on delay (power down with d ll off) t aonpd 2 8,5 2 8,5 ns asynchronous rtt turn - off delay (power down with dll off) t aofpd 2 8,5 2 8,5 ns rtt dynamic change skew t adc 0.3 0.7 0.3 0.7 t ck first dqs, dqs# rising edge t wlmrd 40 - 40 - t ck dqs, dqs# delay t wldqsen 25 - 25 - t ck
preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 11 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ddr 3 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 12800 cl11 10600 cl9 parameter symbol min max min max unit exit reset from cke high to a valid command t xpr max 5nck, t rfc + 10ns - max 5nck, t rfc + 10ns - t ck be gin power supply ramp to power supplies stable t v ddpr - 200 - 200 ms reset# low to power supplies stable t rps 0 200 - 200 ms reset# low to i/o and rtt high - z t ioz - 20 - 20 ns exit precharge power - down to any non - read command t xp max 3nck,6ns - max 3nck ,6ns - t ck cke minimum high/low time t cke max 3nck, 5 ns - max 3nck, 5.625ns - t ck register specifications parameter symbol pins min max units dv supply voltage v dd - 1.425 1.575 v dc reference voltage v ref - 0.49 vdd - 20mv 0.51 vdd + 20mv v dc termination voltage v tt - 0.49 vdd - 20mv 0.51 vdd + 20mv v dc high - level input voltage v ih ( dc ) address, control, command v ref + 100 v dd + 400 mv dc low - level input voltage v il ( dc ) address, control, command - 400 v ref C 100 mv ac high - level input vo ltage v ih ( ac ) address, control, command v ref + 175 v dd + 400 mv ac low - level input voltage v il ( ac ) address, control, command - 400 v ref - 175 mv high - level output current i oh err_out# - t . b . d ma low - level output current i ol err_out# t . b . d t . b . d ma high - level input voltage v ih (cmos) reset#, mirror 0.65 v dd v dd v low - level input voltage v il (cmos) reset#, mirror 0 .3 5 v dd v differential input cross point voltage range v ix (ac) ck, ck#, fbin, fbin# 0.5 v dd - 175mv 0.5 v dd + 175mv v differential i nput voltage v id (ac) ck, ck# 350 t . b . d mv notes: 1. timing and switching specifications for the register listed above are critical for proper operation of the ddr3 sdram rdimms. these are meant to be a subset of the parameters for the specific device use d on the module.
preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 12 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 temperature sensor with serial presence - detect eeprom temperature sensor with serial presence - detect eeprom operating conditions parameter / condition symbol min max units supply voltage v ddspd +3 +3.6 v supply current: vdd = 3.3v i dd +2.0 ma input high voltage: logic 1; scl, sda v ih +1.45 v ddspd +1 v input low voltage: logic 0; scl, sda v il - 550 mv output low voltage: iout = 2.1ma v ol - 400 mv input current i in - 5.0 5.0 a temperature sensing range t . b . d t . b . d c temperatur e sensor accuracy t . b . d t . b . d c sensor and eeprom serial interface timing parameter / condition symbol min max units time bus must be free before a new transition can start t bus 4.7 s sda fall time t f 20 300 ns sda rise time t r 1000 ns data ho ld time t hd:dat 200 900 ns start condition hold time t h:sta 4.0 s clock high period t high 4.0 50 s clock low period t low 4.7 s scl clock frequency f scl 10 100 khz data setup time t su:dat 250 ns start condition setup time t su:sta 4.7 s stop c ondition setup time t su:sto 4.0 s s c l s d a e v e n t s a 2 s a 1 s a 1 s a 0 s a 0 e v e n t w p / r 1 0
preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 13 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 serial presence - detect matrix byte byte description 12800 cl11 10600 cl9 0 crc range, eeprom bytes, bytes used 0x92 1 spd revison 0x1 1 2 dram device type 0x0b 3 module type (form factor) 0x01 4 sdram device den sity & banks 0x0 4 5 sdram device row & column count 0x 21 6 module nominal voltage, v dd 0x00 7 module ranks & device dq count 0x0 1 8 ecc tag & module memory bus width 0x0b 9 fine timebase dividend/divisor 0x 11 10 medium timebase dividend 0x01 11 medi um timebase divisor 0x08 12 min sdram cycle time ( t ck min ) 0x0 a 0x0 c 13 byte 13 reserved 0x00 14 cas latencies supported (cl4 => cl11) 0x fe 0x 7e 15 cas latencies supported (cl12 => cl18) 0x00 16 min cas latency time ( t aa min ) 0x69 17 min write recove ry time ( t wr min ) 0x78 18 min ras# to cas# delay ( t rcd min ) 0x69 19 min row active to row active delay ( t rrd min ) 0x30 20 min row precharge delay ( t rp min ) 0x69 21 upper nibble for t ras & t rc 0x11 22 min active to precharge delay ( t ras min ) 0x 18 0x20 23 min active to active/refresh delay ( t rc min ) 0x8 1 0x89 24 min refresh recovery delay ( t rfc min ) lsb 0x 2 0 25 min refresh recovery delay (t rfc min ) msb 0x0 8 26 min internal write to read cmd delay ( t wtr min ) 0x3c 27 min internal read to precharge cmd delay ( t rtp min ) 0x3c 28 min four active window delay ( t faw min ) msb 0x00 29 min four active window delay ( t faw min ) lsb 0xf0 30 sdram device output drivers supported 0x83 31 sdram device thermal & refresh options 0x0 1
preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 14 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 byte byte description 10600 - 999 8500 - 777 32 ddr3 - module thermal sensor 0x80 33 - 59 bytes 33 - 59 reserved 0x00 60 module height (nominal) 0x0 f 61 module thickness (max) 0x11 62 reference raw card id 0x0 0 63 address mapping edge conector to dram 0x05 64 rdimm thermal heat spreader solution 0x00 65 register mfr id (lsb) 0x04 66 register mfr id (msb) 0xb3 67 register revision number 0x03 68 register type 0x00 69 rc1 (ms nibble) / rc0 (ls nibble) - reserved 0x00 70 rc3 (ms nibble) / rc2 (ls nibble) C drive strength, command/addr ess 0x 00 71 - 116 bytes 71 - 116 reseved 0x00 117 module mfr id (lsb) 0x83 118 module mfr id (msb) 0xda 119 module mfr location id 0x02 germany 120 module mfr year x 121 module mfr week x 122 - 125 module serial number x 126 - 127 crc tbd tbd 128 - 145 modu le part number " sgp04g72a1bd1sa - xx" 146 module die rev x 147 module pcb rev x 148 dram device mfr id (lsb) 0x80 149 dram device mfr (msb) 0x ce 150 - 175 mfr reserved bytes 150 - 175 0x00 176 - 255 customer reserved bytes 176 - 255 0x f f part number code s g p 0 4 g 72 a1 b d 1 sa - d c * r ** 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ** t = thermal sensor *rohs compl. swissbit ag ddr3 - 1 600 mhz sdram d dr 3 24 0 pin registered dimm with parity support chip vendor ( samsung ) capacity ( 4 gb yte ) 1 module rank width chip rev. d pcb - type ( b63rrc a 1 . 20 ) chip organisation x8 * optional / additional information
preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 15 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 revision history revision changes date 0.9 preliminary versi on 16. 01 .201 4
preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 16 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 locations swissbit ag industriestrasse 4 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 03 03 fax: +41 (0)71 913 03 15 _____________________________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany p hone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 _____________________________ swissbit na, inc. 1117 e plaza drive unit e suites 105/205 eagle, id 83616 usa phone: +1 208 258 - 6254 fax: +1 208 938 - 4525 _____________________________ swissbit ja pan, inc. 3f core koenji, 2 - 1 - 24 koenji - kita, suginami - ku, tokyo 166 - 0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512 ________________________________
preliminary data sheet rev.0.9 16.01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 17 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 declaration of conformity we manufacturer: swissbit ag industriestrasse 4 ch - 9552 bronschhofen switzerland declare under our sole responsibility that the product product type: 4 gb ddr3 rdimm brand name: swissmemory? product series: ddr3 rdimms part number: s gp xxx 72 x xxxx - xxxx to which this declaration relates is in conformity with the following directives: 2002/96/ec category 3 (weee) following the provisions of directive restriction of the use of certain hazardous substances 2011/65/eu swissbit ag, january 2014 manuela k?gel head of quality management

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